DICE-Based Flip-Flop With SET Pulse Discriminator on a 90 nm Bulk CMOS Process

In recent years, due to the demand for increased integration and device scaling, integrated circuits (ICs) have been designed with the design rule less than 100 nm. In these ICs, single-event upsets (SEUs) and single-event transients (SETs) are serious problems because their supply voltage and the threshold voltage of the transistors are decreased. A DICE memory cell is said to have excellent tolerance against SEUs. A DICE-based flip-flop with a SET pulse discriminator circuit on a 90-nm bulk CMOS was designed and fabricated. Its improved performance was demonstrated through radiation testing and discussion was made in comparison with a TMR. SEU sensitivity for the angled irradiation was measured and discussed in this study. The test of edge-on irradiation was performed for the first time. The importance of the angled irradiation for the memory cells that have redundant memory nodes was demonstrated.