DocumentCode :
1394814
Title :
Ionizing dose hardness assurance methodology for qualification of a BiCMOS technology dedicated to high dose level applications
Author :
Flament, O. ; Musseau, O. ; Leray, J.L. ; Dutisseuil, E. ; Corbiere, T.
Author_Institution :
CEA, Bruyeres-le-Chatel, France
Volume :
45
Issue :
3
fYear :
1998
fDate :
6/1/1998 12:00:00 AM
Firstpage :
1420
Lastpage :
1424
Abstract :
This work concerns the development of a radiation hardness assurance methodology specially devoted to CMOS, JFET and bipolar transistors used in high total dose level environments. On the basis of recent studies, high temperature, high dose rate irradiations were performed. We propose a test procedure which combines high temperature irradiations and isochronal anneals for the qualification
Keywords :
BiCMOS integrated circuits; annealing; integrated circuit testing; radiation hardening (electronics); BiCMOS technology; CMOS transistor; JFET transistor; bipolar transistor; high temperature irradiation; ionizing dose hardness assurance methodology; isochronal annealing; qualification; Annealing; BiCMOS integrated circuits; Bipolar transistors; Degradation; MOS devices; MOSFETs; Qualifications; Space technology; Temperature; Testing;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/23.685217
Filename :
685217
Link To Document :
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