All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of $-{\hbox {0.7}} ~^{\circ}{\hbox {C}}-+{\hbox {0.6}}~^{\circ}{\hbox {C}}$ After One-Poi

To get rid of the heavy burden of aspect ratio tuning, bias adjustment and porting problem among processes in full-custom or mixed-mode design, a fully digital smart temperature sensor realizable with 140 field programmable gate array (FPGA) logic elements was proposed for painless VLSI on-chip integrations. By simply replacing the cyclic delay line with a retriggerable ring oscillator for accuracy enhancement, modifying the gain of time amplifier from fixed to variable for one-point calibration support and adopting a second-order master curve for curvature correction in this paper, the proposed smart temperature sensor can achieve two thirds reduction in circuit size, at least four-fold improvement in power consumption and more than two-fold enhancement in accuracy. To demonstrate the performance under practical process variation, the sensor realized with as few as 48 FPGA logic elements for rapid prototyping was measured over 0°C to 100°C range for 20 test chips from batches spreading over 4 years. The measured inaccuracy is -0.7°C-+0.6°C which is superior to -1.8°C-+2.3°C of its full-custom predecessor with a third-order master curve and five test samples from one single batch. The accuracy is even better than those of full-custom sensors with two-point calibration. The conversion rate is around 4.4 kHz and the power consumption can be reduced to 175 nJ per conversion by increasing the number of delay stages in ring oscillator to 4608.