Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric

Author

Yeo, Yee Chia ; Lu, Qiang ; Lee, Wen Chin ; King, Tsu-Jae ; Hu, Chenming ; Wang, Xiewen ; Guo, Xin ; Ma, T.P.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

21

Issue

11

fYear

2000

Firstpage

540

Lastpage

542

Abstract

We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si/sub 3/N/sub 4/ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications.

Keywords

CMOS integrated circuits; MOSFET; dielectric thin films; leakage currents; low-power electronics; semiconductor device models; silicon compounds; tunnelling; vapour deposited coatings; 1.42 nm; CMOSFET; MOSFETs; NMOSFET; PMOSFETs; Si/sub 3/N/sub 4/; barrier potentials; direct tunneling gate leakage current; electron tunneling mass; high-performance low-power applications; hole tunneling mass; jet-vapor deposition; maximum tolerable direct tunneling gate current; scaling limits; semi-empirical model; supply voltages; tunneling mechanisms; ultrathin Si/sub 3/N/sub 4/ gate dielectric; CMOS technology; Charge carrier processes; Dielectrics; Leakage current; MOSFETs; Permittivity; Semiconductor device modeling; Silicon; Tunneling; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.877204

Filename

877204