Low-power wireless video systems

Author

Meng, Teresa U.

Author_Institution

Stanford Univ., CA, USA

Volume

36

Issue

6

fYear

1998

fDate

6/1/1998 12:00:00 AM

Firstpage

130

Lastpage

136

Abstract

This article presents the design principles for implementing low-power wireless video systems through the use of two examples, a single-chip digital video camera and a wireless video-on-demand system. The discussion focuses on the architectural and circuit techniques developed specifically for silicon integration of high-performance low-power wireless video systems. The proposed single-chip digital camera incorporates a parallel architecture to perform MPEG-2 encoding in real time, while the video-on-demand system employs an error-resilient compression algorithm to guard against the transmission errors often encountered in wireless communication. Both wireless video systems, one for encoding and the other for decoding, dissipate only tens of milliwatts of power, achieving a power reduction two orders of magnitude below standard solutions

Keywords

CMOS digital integrated circuits; decoding; digital signal processing chips; digital television; interactive video; parallel architectures; vector quantisation; video cameras; video coding; visual communication; Si; VQ decoder; decoding; error-resilient compression algorithm; low power wireless video systems; parallel architecture; power reduction; real time MPEG-2 encoding; silicon integration; single-chip digital video camera; transmission errors; wireless communication; wireless video-on-demand system; Circuits; Compression algorithms; Digital cameras; Encoding; Parallel architectures; Real time systems; Silicon; Transform coding; Video compression; Wireless communication;

fLanguage

English

Journal_Title

Communications Magazine, IEEE

Publisher

ieee

ISSN

0163-6804

Type

jour

DOI

10.1109/35.685376

Filename

685376