A Fast ULV Logic Synthesis Flow in Many- $V_{t}$ CMOS Processes for Minimum Energy Under Timing Constraints

Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (V_dd) and threshold (V_t) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the V_dd/V_t MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all V_dd/V_t pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC´99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4× compared to a conventional flow with V_dd scaling only.