DocumentCode
1397849
Title
The MIPS R3010 floating-point coprocessor
Author
Rowen, C. ; Johnson, Mark ; Ries, Paul
Author_Institution
MIPS Comput. Syst., Sunnyvale, CA, USA
Volume
8
Issue
3
fYear
1988
fDate
6/1/1988 12:00:00 AM
Firstpage
53
Lastpage
62
Abstract
A description is given of the R3010 floating-point accelerator chip, a coprocessor that is based on advanced reduced-instruction-set-computer (RISC) architecture and VLSI design techniques and provides high-speed floating-point operation. The 75000-transistor hard-wired chip executes four instructions in parallel. Its performance is compared with that of available floating-point processors and its architecture is examined. The organization and implementation of the R3010 is discussed.<>
Keywords
VLSI; digital arithmetic; microprocessor chips; reduced instruction set computing; MIPS R3010 floating-point coprocessor; VLSI design techniques; floating-point accelerator chip; reduced-instruction-set-computer; Application software; Computer architecture; Coprocessors; Delay; Floating-point arithmetic; Hardware; Reduced instruction set computing; Registers; Systems engineering and theory; Very large scale integration;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/40.540
Filename
540
Link To Document