A PLL-based frequency synthesizer for 160-MHz double-sampled SC filters

Author

Rezzi, F. ; Montecchi, F. ; Castello, R.

Author_Institution

Dipartimento di Elettronica, Pavia Univ., Italy

Volume

31

Issue

10

fYear

1996

fDate

10/1/1996 12:00:00 AM

Firstpage

1560

Lastpage

1564

Abstract

This paper describes a clock generator for a double-sampled switched capacitor (SC) filtering system. The circuit is based on a fast charge-pump phase-locked loop (PLL) system that multiplies an external reference clock signal by a factor of eight and also ensures a high precision and stability of two internal nonoverlapped clock phases up to 80 MHz. This allows the driving of double-sampled SC filters up to 160 MHz sampling rate. The PLL is a third-order system with a bandwidth of 100 kHz and a lock-in time of 15 μs. The output clock jitter is 170 ps r.m.s. The total power consumption at 160 MHz is 25 mW and the total chip area is about 1 mm²

Keywords

BiCMOS digital integrated circuits; digital phase locked loops; frequency synthesizers; sampled data filters; switched capacitor filters; timing circuits; 100 kHz; 15 mus; 160 MHz; 25 mW; 80 MHz; PLL-based frequency synthesizer; clock generator; double-sampled SC filters; fast charge-pump PLL system; high precision; phase-locked loop system; stability; switched capacitor filtering system; third-order system; Bandwidth; Capacitors; Charge pumps; Circuit stability; Clocks; Filtering; Filters; Frequency synthesizers; Phase locked loops; Sampling methods;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.540069

Filename

540069