Systolic decoder for burst error-correcting codes

The author develops a new systolic architecture for the decoding of single-burst error-correcting cyclic codes (SBECCC). The well known decoding procedure for these codes, based on the error-trapping technique, is expressed by means of uniform recurrence equations to be implemented using systolic arrays. The decoder uses the generator polynomial of the code. For a (n,k) SBECCC, with a burst-error correcting capability l, the decoder consists of (n+k-1) cells arranged into a serial-in serial-out one-dimensional feed-forward systolic array. The decoder has the following advantages: it does not contain any feedback connection; it is easily reconfigurable for variable code parameters n, k and l and changes in the choice of the generator polynomial