DocumentCode :
1398399
Title :
Address Translation Aware Memory Consistency
Author :
Romanescu, Bogdan F. ; Lebeck, Alvin R. ; Sorin, Daniel J.
Volume :
31
Issue :
1
fYear :
2011
Firstpage :
109
Lastpage :
118
Abstract :
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need.
Keywords :
program debugging; virtual storage; address translation aware memory consistency; bug detection; computer system; design bug; runtime fault; virtual memory; Memory consistency; address translation; dynamic verification; virtual memory;
fLanguage :
English
Journal_Title :
Micro, IEEE
Publisher :
ieee
ISSN :
0272-1732
Type :
jour
DOI :
10.1109/MM.2010.99
Filename :
5661753
Link To Document :
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