Application of a systolic macrocell-based VLSI design style to the design of a single-chip high-performance FIR filter

Author

Roncella, R. ; Saletti, R. ; Terreni, P. ; Piatelli, D.

Author_Institution

Centro di Studio per Metodi e Dispositivi per Radiotrasmissioni, Pisa, Italy

Volume

138

Issue

1

fYear

1991

fDate

2/1/1991 12:00:00 AM

Firstpage

17

Lastpage

21

Abstract

Presents the application of a VLSI design style based on systolic macrocells in the realisation of a single-chip high-performance digital FIR filter. The systolic macrocell design style is well suited for the design of high-performance integrated circuits to be used in digital signal processing. The style uses as design primitives bit-level systolic macrocells designed according to logical and electrical rules that guarantee the required performance. The filter was designed with a 1.5 μm CMOS technology; it occupies an area of 3.74×3.42 mm² and has 128 coefficients. The expected clock frequency is of about 100 MHz and allows a throughput of the order of 1 million samples per second. The technique applied to the design of the most critical part of the circuit (the clock generation and distribution network) is also described

Keywords

CMOS integrated circuits; VLSI; computerised signal processing; digital filters; digital integrated circuits; network synthesis; systolic arrays; 1.5 micron; 100 MHz; CMOS technology; VLSI design style; bit-level systolic macrocells; circuit design; clock frequency; clock generation; digital signal processing; distribution network; electrical rules; high-performance integrated circuits; logical rules; single-chip digital FIR filter;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings G

Publisher

iet

ISSN

0956-3768

Type

jour

Filename

87804