Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A programmable edge-combining delay-locked loop (DLL) with fast switching transient and reduced output spur is presented in this work. With 12 delay cells adopted in the DLL, the programmable frequency-multiplied output can be quickly switched between ×6, ×3, and ×2 without affecting the lock state of the DLL. Output spur is suppressed by reducing the DLL phase offset in the lock state, which is achieved by decreasing the charge-pump (CP) current during the idle interval of the phase detector. The proposed DLL frequency synthesizer, which has been realized in a CMOS 90-nm technology, consumes 20 mW at 1.2 V supply with the frequency-multiplied output covering from 0.45 to 5.4 GHz. For 850-MHz input clock, the phase noise at 1-MHz frequency offset after ×6, ×3, and ×2 is -121.4, -127.4, and -129.7 dBc/Hz, respectively. The corresponding output spurs achieve -26.2, -36.8, and -39.2 dBc for ×6, ×3, and ×2, which are 7.6, 5.9, and 15.4 dB lower than those using a conventional current-steering CP, respectively.
Keywords :
CMOS integrated circuits; charge pump circuits; clocks; delay lock loops; frequency synthesizers; integrated circuit noise; phase detectors; phase noise; CMOS technology; DLL frequency synthesizer; DLL phase offset; charge-pump current; current-splitting charge pump; delay cell; frequency 0.45 GHz to 5.4 GHz; frequency 1 MHz; frequency 850 MHz; input clock; phase detector; phase noise; power 20 mW; programmable edge-combining delay-locked loop; programmable frequency-multiplied output; size 90 nm; spur suppression; switching transient; voltage 1.2 V; Charge pumps; Frequency synthesizers; Phase locked loops; Pulse generation; Tracking loops; Voltage control; Charge pump (CP); current mismatch; delay-locked loop (DLL); edge combiner; frequency multiplier; frequency synthesizer; phase-locked loop (PLL); spur;
