Sectioning and fault analysis of junction transistors

Special techniques have recently been developed by the authors to enable microsections to be readily made on high-frequency p-n-p and p-n-i-p junction transistors. It is impossible to use standard metallographic techniques when sectioning these devices, owing to the extreme fragility of the very thin germanium wafers used in their fabrication. Wafers as thin as 0.001 in may be encountered, and it has been found necessary to encapsulate the specimens in two stages, using different resins, to ensure adequate support of the wafer edges and so avoid chipping of the wafers during the subsequent grinding and polishing operations. A detailed grinding and polishing procedure has been developed to give optimum surface finish. The junction structure can finally be shown up by preferential etching. After preparation, the specimens can be microscopically examined, photographed and much valuable information extracted concerning the wetting, alloy penetration, recrystallization, crystal orientation and junction geometry. It is possible to examine the effect of the final clean-up etch used during manufacture, and in some cases to explain soft reverse-junction characteristics. The paper describes the preparation of large numbers of sections on a routine basis, using these techniques, and a number of examples are shown and typical faults discussed. The information obtained from these samples has proved of considerable value, particularly during the early stages of any new development.