DocumentCode
1399104
Title
Test pattern generation for logic crosstalk faults in VLSI circuits
Author
Rubio, A. ; Sainz, J.A. ; Kinoshita, K.
Author_Institution
Dept. of Phys., Univ. of the Illes Balears, Palma, Spain
Volume
138
Issue
2
fYear
1991
fDate
4/1/1991 12:00:00 AM
Firstpage
179
Lastpage
181
Abstract
Investigates test pattern generation (TPG) for logic circuits in which transient logic errors are likely to be produced by crosstalk interference between nodes. Algebraic and algorithmic approaches for TPG of combinational circuits are presented and applied to several example circuits
Keywords
VLSI; combinatorial circuits; crosstalk; fault location; integrated logic circuits; logic testing; TPG; VLSI circuits; combinational circuits; crosstalk interference; logic circuits; logic crosstalk faults; test pattern generation; transient logic errors;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings G
Publisher
iet
ISSN
0956-3768
Type
jour
Filename
87830
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