Charge injection of analogue CMOS switches

The clock-feedthrough phenomenon in sample-and-hold circuits using complementary MOS transistor switches is discussed in detail. The analysis starts with a generalised clock-feedthrough formula for the single MOS switch and is extended to a discussion of the basic CMOS sample-and-hold circuit operated over a wide signal and clock delay range. Simple formulas for the estimation of the clock feedthrough voltages are given. Experimental results obtained with custom integrated test chips realised with a 3 μm CMOS process are reported and found to be in good agreement with the theory. Simultaneous switching of transistor pairs with identical geometry at slow speed is recommended for optimal clock-feedthrough performance in CMOS switches