DocumentCode :
1399471
Title :
Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length
Author :
Khakifirooz, Ali ; Cheng, Kangguo ; Reznicek, Alexander ; Adam, Thomas ; Loubet, Nicolas ; He, Hong ; Kuss, James ; Li, Juntao ; Kulkarni, Pranita ; Ponoth, Shom ; Sreenivasan, Raghavasimhan ; Liu, Qing ; Doris, Bruce ; Shahidi, Ghavam
Author_Institution :
IBM Res., Albany, NY, USA
Volume :
33
Issue :
2
fYear :
2012
Firstpage :
149
Lastpage :
151
Abstract :
We report high-performance extremely thin SOI MOSFETs fabricated with a channel thickness down to 3.5 nm, sub-20-nm gate length, and contacted gate pitch of 100 nm. At an effective channel length of 18 nm, a drain-induced barrier lowering of 100 mV is achieved by either thinning the channel to 3.5 nm or by applying a reverse back-gate bias to 6-nm channel MOSFETs. Moreover, minimal increase in series resistance is seen when the channel is scaled to 3.5 nm, resulting in no performance degradation with SOI thickness scaling.
Keywords :
MOSFET; nanotechnology; silicon-on-insulator; ETSOI; SOI thickness scaling; drain induced barrier lowering; extremely thin SOI MOSFET scalability; size 100 nm; size 3.5 nm; Logic gates; MOSFETs; Performance evaluation; Resistance; Scalability; Very large scale integration; Epitaxy; extremely thin SOI (ETSOI); fully depleted SOI; raised source/drain;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2011.2174411
Filename :
6104351
Link To Document :
بازگشت