Title :
Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects
Author :
Chen, Kai ; Hu, Chenming ; Fang, Peng ; Lin, Min Ren ; Wollesen, Donald L.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
11/1/1997 12:00:00 AM
Abstract :
Sub-quarter micron MOSFET´s and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted
Keywords :
CMOS digital integrated circuits; MOSFET; carrier mobility; delays; integrated circuit interconnections; integrated circuit modelling; 1.5 to 3.3 V; 2.5 to 6 nm; CMOS; current model; gate delay; gate oxide; interconnect loading; interconnect loading effects; parasitic series resistance; ring oscillators; sub-quarter micron MOSFET; supply voltages; universal mobility model; velocity saturation; voltage scaling; Capacitance; Charge carrier processes; Equations; MOSFET circuits; Predictive models; Propagation delay; Ring oscillators; Semiconductor device modeling; Voltage; Voltage-controlled oscillators;
Journal_Title :
Electron Devices, IEEE Transactions on
