Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

Author

Chen, Kai ; Hu, Chenming ; Fang, Peng ; Lin, Min Ren ; Wollesen, Donald L.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

44

Issue

11

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

1951

Lastpage

1957

Abstract

Sub-quarter micron MOSFET´s and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. I_dsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted

Keywords

CMOS digital integrated circuits; MOSFET; carrier mobility; delays; integrated circuit interconnections; integrated circuit modelling; 1.5 to 3.3 V; 2.5 to 6 nm; CMOS; current model; gate delay; gate oxide; interconnect loading; interconnect loading effects; parasitic series resistance; ring oscillators; sub-quarter micron MOSFET; supply voltages; universal mobility model; velocity saturation; voltage scaling; Capacitance; Charge carrier processes; Equations; MOSFET circuits; Predictive models; Propagation delay; Ring oscillators; Semiconductor device modeling; Voltage; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.641365

Filename

641365