DocumentCode :
1399985
Title :
Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors
Author :
Neviani, Andrea ; Pavan, Paolo ; Nardi, Alessandra ; Chantre, Alain ; Vendrame, Loris ; Zanoni, Enrico
Author_Institution :
Dipt. di Elettronica e Inf., Padova Univ., Italy
Volume :
44
Issue :
11
fYear :
1997
fDate :
11/1/1997 12:00:00 AM
Firstpage :
2059
Lastpage :
2063
Abstract :
The authors present the results of several accelerated tests performed on self-aligned, etched-polysilicon, npn bipolar transistors with silicon dioxide emitter spacers, and propose a new technique for the characterization of the electric field at the periphery (i.e. at the interface between silicon and the silicon dioxide spacer) of the base-emitter junction. Tests are performed reverse-biasing at constant current the base-emitter junction (with floating collector) both in the tunneling and avalanche regimes. The results are found to be in good agreement with existing degradation models, and show that degradation kinetics may depend to some extent on device layout, particularly in the avalanche regime. The influence of charge injection in the oxide on degradation kinetics is also analyzed and compared to the predictions of an existing model. A new method for estimating charge injection in the oxide is proposed; the method consists in evaluating the decrease of the electric field at the periphery of the device by measuring the temperature dependence of the tunneling component of reverse base current. The electric field behavior is then compared to the degradation dependence on stress time in the different stress regimes
Keywords :
avalanche breakdown; bipolar transistors; elemental semiconductors; hot carriers; life testing; semiconductor device reliability; semiconductor device testing; silicon; sputter etching; tunnelling; RIE; Si-SiO2; SiO2 emitter spacers; accelerated tests; avalanche regime; base-emitter junction; charge injection; degradation kinetics; hot-carrier degradation; model; oxide charge build-up; peripheral electric field; reverse base current; reverse-biasing; self-aligned etched-polysilicon npn bipolar transistors; stress time; temperature dependence; tunneling regime; Automatic testing; Degradation; Etching; Hot carriers; Kinetic theory; Life estimation; Performance evaluation; Silicon compounds; Stress; Tunneling;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.641384
Filename :
641384
Link To Document :
بازگشت