Title :
A high performance 16 Mb DRAM using giga-bit technologies
Author :
Jeong, Gi-Tae ; Lee, Kyu-Chan ; Ha, Dae-Won ; Lee, Kyu-Hyun ; Kim, Kyung-Hoon ; Kim, Il-Gu ; Kim, Do-Hyung ; Kim, Kinam
Author_Institution :
Technol. Dev., Samsung Electron. Co., Kyungki-Do, South Korea
fDate :
11/1/1997 12:00:00 AM
Abstract :
An experimental high performance 16 Mb Dynamic Random Access Memory (DRAM) having a 0.18 μm design rule for gigabit DRAM´s was developed. Junction leakage current and junction capacitance were reduced by shallow trench isolation (STI). A fast access time even at low operation voltage (1.5 V) was achieved by using a TiSi2 gate and new circuit techniques. Large sensing margin and stable operation were achieved by using a new dielectric material (Ta2 O5) in the cell capacitor. Insufficient depth of focus margin for the back-end of line process was overcome by a triple metallization scheme with one W and two Al metals. With these new technologies, a high speed of 28 ns row address access time (Trac ) at 1.5 V and a small chip size of 5.3×5.4 mm2 were achieved
Keywords :
CMOS memory circuits; DRAM chips; capacitance; circuit stability; dielectric thin films; integrated circuit design; integrated circuit measurement; integrated circuit metallisation; isolation technology; leakage currents; 0.18 mum; 1.5 V; 16 Mbit; 28 ns; Al-W-Al; CMOS; Ta2O5; TiSi2; TiSi2 gate technique; access time; cell capacitor; chip size; depth of focus margin; design rule; dielectric material; giga-bit technologies; high performance DRAM; junction capacitance; junction leakage current; low operation voltage; operational stability; row address access time; sensing margin; shallow trench isolation; triple metallization scheme; Capacitance; Capacitors; Circuits; DRAM chips; Dielectric materials; Isolation technology; Leakage current; Low voltage; Metallization; Random access memory;
Journal_Title :
Electron Devices, IEEE Transactions on
