Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation

This paper analyzes and compares the stability, margin, performance, and variability of ultrathin-body (UTB) SOI 6T SRAM cells operating near the subthreshold region with different threshold voltage (V_th) design. Our results indicate that UTB SOI 6T SRAM cell using low V_th devices (|V_th| = 0.19 V) shows a comparable read static noise margin (RSNM), 41% improvement in σRSNM, 84% improvement in write static noise margin (WSNM), and 67% improvement in σWSNM as compared with the case using higher V_th devices (|V_th| = 0.49 V). As V_th decreases (work function moves to the band edge), the “cell” access time improves significantly with correspondingly higher standby leakage. For low V_th devices (|V_th| = 0.19 V), it is shown that lowering bit-line precharge voltage by 50 mV reduces the standby leakage by 20%. Our study suggests that the lower V_th devices operating slightly into super-threshold region improve the stability/variability significantly and offer higher performance for ultralow voltage SRAM applications.