Hardware implementation of CMAC neural network with reduced storage requirement

Author

Ker, Jar-Shone ; Kuo, Yau-Hwang ; Wen, Rong-Chang ; Liu, Bin-Da

Author_Institution

Dept. of Electron. Eng., Kao Yuan Jr. Coll. of Technol. & Commerce, Kaohsiung, Taiwan

Volume

8

Issue

6

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

1545

Lastpage

1556

Abstract

The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100%. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture

Keywords

CMOS integrated circuits; cerebellar model arithmetic computers; image colour analysis; neural chips; neural net architecture; pipeline processing; CMAC neural network; cerebellar model articulation controller; color calibration; direct weight address mapping; pipeline architecture; storage space; weight memory; Brain modeling; Calibration; Computer architecture; Computer networks; Convergence; Neural network hardware; Neural networks; Pipelines; Prototypes; Space technology;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.641476

Filename

641476