Prioritised ATM switches on board satellites: architectural analysis and design

Global broadband networking is an emerging technology aiming at providing broadband services all over the world using a constellation of satellites with on-board ATM switching capabilities. The authors propose an architecture for the ATM switches to be used on board satellites and identify both performance and physical requirements that make them distinct from terrestrial switches. Based on these requirements, a shared memory architecture is proposed. A major aspect of the switch design is the buffer management controller and the way it provides QoS to several classes of loss and delay priority traffic. A circular sorting queue is proposed as an efficient solution in terms of performance and implementation. It is also analysed using an M/G/1/K model and a supplementary variable method. This analysis is used to estimate the buffer size required and to evaluate the performance of the architecture. Some implementation guidelines for satellite switches are also discussed along with a low-power VLSI implementation of the circular queue