Title :
A reconfigurable tree architecture with multistage interconnection network
Author :
Biswas, Nripendra N. ; Srinivas, S.
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
fDate :
12/1/1990 12:00:00 AM
Abstract :
A novel approach to the design of a reconfigurable tree architecture is presented. The architecture is implemented with an augmented shuffle-exchange multistage interconnection network and is capable of assuming N distinct binary tree configurations, where N is the number of processing elements (PEs) in the system. The novel features of the architecture include fast switching from one configuration to another, simplified hardware in the PEs and the switching network, and simple routing control
Keywords :
computer architecture; multiprocessor interconnection networks; augmented shuffle-exchange; distinct binary tree configurations; multistage interconnection network; processing elements; reconfigurable tree architecture; routing control; switching network; Arithmetic; Computer architecture; Fault detection; Iterative methods; Logic arrays; Logic testing; Multiprocessor interconnection networks; Switches; Systolic arrays; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
