Title :
Fault detection and design complexity in C-testable VLSI arrays
Author :
Lombardi, F. ; Huang, W.-K.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fDate :
12/1/1990 12:00:00 AM
Abstract :
An extension of a previous approach to fault detection and C -testability of orthogonal iterative arrays is presented. The state transition table of a basic cell is analyzed. Five new states are added to it. It is proved that even though the number of additional states in the proposed approach is greater than previous approaches, (five states compared to four), the required number of test vectors is considerably reduced (by a factor of approximately 4/9). An approach to implement the proposed C-testability approach into logic design is also presented. Complexity of this implementation is analyzed
Keywords :
VLSI; logic arrays; logic testing; C-testable VLSI arrays; design complexity; fault detection; logic design; orthogonal iterative arrays; state transition table; test vectors; Chebyshev approximation; Clocks; Delay estimation; Fault detection; Monte Carlo methods; Random variables; Solid modeling; Upper bound; Very large scale integration; Wires;
Journal_Title :
Computers, IEEE Transactions on
