Automatic Compensation of the Voltage Attenuation in 3-D Interconnection Based on Capacitive Coupling

An architecture to compensate the voltage attenuation introduced by 3-D capacitive coupling is proposed. The scheme is based on a calibration channel which sets the gain of the variable gain amplifiers of the signal channels in such a way as to compensate for the voltage attenuation. Based on this architecture, a prototype has been designed aimed at demonstrating that 3-D technology based on capacitive coupling allows one to transmit analog signals as well as digital ones. CMOS 90 nm technology was used and 3-D assembly is done at die level using a face to face stacking procedure. The area of each signal channel and of the calibration channel is 90 × 30 μm² and 138 × 191 μm², respectively, with a power consumption of 1 mW and 3.6 mW. A gain error within 10% of the nominal value was measured for signal amplitudes varying from 200 mV to 1 V in the 100 kHz to 20 MHz range.