Title :
Diagnosing realistic bridging faults with single stuck-at information
Author :
Lavo, David B. ; Chess, Brian ; Larrabee, Tracy ; Ferguson, F. Joel
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
fDate :
3/1/1998 12:00:00 AM
Abstract :
Successful failure analysis requires accurate fault diagnosis. This paper presents a method for diagnosing bridging faults that improves on previous methods. The new method uses single stuck-at fault signatures, produces accurate and precise diagnoses, and takes into account imperfect fault modeling; it accomplishes this by introducing the concepts of match restriction, match requirement, and match ranking
Keywords :
CMOS logic circuits; automatic testing; failure analysis; fault diagnosis; integrated circuit testing; logic testing; bridging faults; failure analysis; fault diagnosis; imperfect fault modeling; match ranking; match requirement; match restriction; single stuck-at information; stuck-at fault signatures; Cause effect analysis; Circuit faults; Circuit synthesis; Circuit testing; Failure analysis; Fault diagnosis; Fault location; Logic circuits; Logic testing; Production;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
