Abstract :
This issue of IEEE Design & Test of Computers (D&T) is focused on the theme of smarter silicon for achieving predictable performance and high reliability without the need for significant guard banding. Guest Editors Mohammad Tehranipoor and LeRoy Winemberg have taken the initiative and worked diligently to put together this special issue with a set of five selected articles, which include contributions by experts from both academia and industry. These articles cover a number of aspects of smarter silicon, including onchip structures for monitoring aging, voltage and frequency scaling to proactively prevent errors, a study of the relationship between performance degradation and operating conditions, optimization of SerDes, and hardware Trojan detection. This issue of D&T also includes the annual International Test Conference (ITC) special section. Candidate papers were selected from ITC 2011 and they went through the regular D&T review process. After review, three papers were selected for inclusion in the ITC special section. A fourth paper from ITC 2011 is being published as a "prize paper." The paper titled "Physically-Aware Analysis of Systematic Defects in Integrated Circuits" is based on the PhD thesis of Chiu-Wing (Jason) Tam, who won the E. J. McCluskey Best 2012 Doctoral Thesis Award in 2011.
