A 256-Mb SDRAM using a register-controlled digital DLL

Author

Hatakeyama, Atsushi ; Mochizuki, Hirohiko ; Aikawa, Tadao ; Takita, Masato ; Ishii, Yuki ; Tsuboi, Hironobu ; Fujioka, Shin-Ya ; Yamaguchi, Shusaku ; Koga, Makoto ; Serizawa, Yuji ; Nishimura, Koichi ; Kawabata, Kuninori ; Okajima, Yoshinori ; Kawano, Mic

Author_Institution

Dept. of Memory Design, Fujitsu Ltd., Kawasaki, Japan

Volume

32

Issue

11

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

1728

Lastpage

1734

Abstract

This paper describes the key technologies used in a 256-Mb synchronous DRAM with a clock access time of 1 ns. This DRAM is stable against temperature, voltage, and process variation through the use of a register-controlled digital delay-locked loop (RDLL). The total timing error of the RDLL is about 0.4 ns, sufficient for high frequency operation at 150 to 200 MHz. Unlike most conventional high-density DRAMs, the bit lines are placed above the storage capacitors in this DRAM to relax the design rules of the core area. The noise issues were analyzed and resolved to help implement the technology for mass production of 0.28- to 0.24-μm 200-MHz DRAMs

Keywords

CMOS memory circuits; DRAM chips; circuit stability; delay circuits; integrated circuit design; integrated circuit noise; 0.24 to 0.28 micron; 1 ns; 150 to 200 MHz; 256 Mbit; digital delay-locked loop; high frequency operation; high-density DRAM; mass production; noise issues; register-controlled digital DLL; synchronous DRAM; Capacitors; Clocks; Delay; Frequency; Mass production; Random access memory; SDRAM; Temperature; Timing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.641693

Filename

641693