A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O

Author

Nakamura, Kazuyuki ; Takeda, Koichi ; Toyoshima, Hideo ; Noda, Kenji ; Ohkubo, Hiroaki ; Uchida, Tetsuya ; Shimizu, Toshiyuki ; Itani, Toshiro ; Tokashiki, Ken ; Kishimoto, Koji

Author_Institution

Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan

Volume

32

Issue

11

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

1758

Lastpage

1765

Abstract

A 32-b 500-MHz 4-1-1-1 operation 4-Mb pipeline burst cache SRAM has been developed. In order to achieve both high bandwidth operation and short latency operation, we developed the following technologies: 1) a prefetched pipeline-burst scheme with double late-write buffers, 2) gate size reduction and a bit-line equalization by source resetting, 3) point-to-point bidirectional coding I/O´s to reduce bus noise and power consumption, and 4) a three-level metal 0.25-μm CMOS process technology with six transistor memory cells

Keywords

CMOS memory circuits; SRAM chips; cache storage; integrated circuit noise; 0.25 micron; 32 bit; 4 Mbit; 500 MHz; CMOS SRAM; bit-line equalization; bus noise reduction; double late-write buffers; gate size reduction; high bandwidth operation; pipeline-burst cache SRAM; point-to-point noise reduction coding I/O; power consumption reduction; prefetched pipeline-burst scheme; short latency operation; six transistor memory cells; source resetting; static RAM; three-level metal CMOS process technology; Bandwidth; CMOS technology; Central Processing Unit; Delay; Energy consumption; Frequency; Noise reduction; Pipelines; Prefetching; Random access memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.641698

Filename

641698