A 160-MHz analog equalizer for magnetic disk read channels

Author

Kiriaki, Sami ; Viswanathan, Lakshmi T. ; Feygin, Gennady ; Staszewski, Bogdan ; Pierson, Richard ; Krenik, Bill ; De Wit, Michiel ; Nagaraj, Krishnaswamy

Author_Institution

Hard Disk Drive Group, Texas Instrum. Inc., Dallas, TX, USA

Volume

32

Issue

11

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

1839

Lastpage

1850

Abstract

This paper presents a 160-MHz five-tap adaptive analog equalizer for magnetic recording disk drive read channels. The design is based on a direct form finite impulse response (FIR) architecture which includes four key features: signal shuffling in the analog domain to improve noise performance, use of a master sample-and-hold stage to improve the dynamic performance and clock jitter of the clock recovery loop, use of an additional sample-and-hold stage to accommodate settling time requirements and reduce power, and use of a time interleaved sign-sign LMS algorithm which permits coefficient adaptation at low power and area. This equalizer occupies 1.36 mm² and consumes only 240 mW with 5-V supply voltage. It is fabricated in BiCMOS technology with 0.8-μm CMOS and 0.72-μm² NPN, 3LM, and DP capacitor

Keywords

BiCMOS analogue integrated circuits; adaptive equalisers; analogue processing circuits; hard discs; jitter; least mean squares methods; 0.72 micron; 0.8 micron; 160 MHz; 240 mW; 5 V; BiCMOS technology; analog equalizer; clock jitter; clock recovery loop; direct form FIR architecture; dynamic performance; magnetic disk read channels; noise performance; sample/hold stage; signal shuffling; time interleaved sign-sign LMS algorithm; Algorithm design and analysis; CMOS technology; Clocks; Disk drives; Equalizers; Finite impulse response filter; Magnetic domains; Magnetic recording; Noise reduction; Signal design;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.641708

Filename

641708