A new RSA cryptosystem hardware design based on Montgomery´s algorithm

Author

Yang, Ching-Chao ; Chang, Tian-Sheuan ; Jen, Chein-Wei

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

45

Issue

7

fYear

1998

fDate

7/1/1998 12:00:00 AM

Firstpage

908

Lastpage

913

Abstract

In this paper, we propose a new algorithm based on Montgomery´s algorithm to calculate modular multiplication that is the core arithmetic operation in an RSA cryptosystem. The modified algorithm eliminates over large residue and has very short critical path delay that yields a very high speed processing. The new architecture based on this modified algorithm takes about 1.5n² clock cycles on the average to finish one n-bit RSA operation. We have implemented a 512-bit single-chip RSA processor based on the modified algorithm with Compass 0.6-μm SPDM CMOS cell library. The simulation results show that the processor can operate up to 125 MHz and deliver the baud rate of 164 Kbits/s on the average

Keywords

CMOS digital integrated circuits; digital arithmetic; digital signal processing chips; public key cryptography; 0.6 micron; 125 MHz; 164 Kbit/s; Compass SPDM CMOS cell library; Montgomery algorithm; RSA cryptosystem hardware design; arithmetic operation; high speed processing; modified algorithm; modular multiplication; single-chip RSA processor; Algorithm design and analysis; Application software; Circuits; Clocks; Data security; Digital arithmetic; Hardware; Notice of Violation; Public key cryptography; Signal processing algorithms;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.700944

Filename

700944