• DocumentCode
    1403030
  • Title

    High Performance Phylogenetic Analysis With Maximum Parsimony on Reconfigurable Hardware

  • Author

    Kasap, Server ; Benkrid, Khaled

  • Author_Institution
    Sch. of Eng., Univ. of Edinburgh, Edinburgh, UK
  • Volume
    19
  • Issue
    5
  • fYear
    2011
  • fDate
    5/1/2011 12:00:00 AM
  • Firstpage
    796
  • Lastpage
    808
  • Abstract
    We present in this paper the detailed field-programmable gate-array (FPGA) design of the Maximum Parsimony method for molecular-based phylogenetic analysis and its implementation on the nodes of an FPGA supercomputer called Maxwell. This is the first FPGA implementation of this method for nucleotide sequence data reported in the literature. The hardware architecture consists in a linear systolic array composed of 20 processing elements each of which performing Sankoff´s algorithm for a different tree topology in parallel. This array computes the scores of all theoretically possible trees for a given number of taxa in several iterations. The currently supported maximum number of taxa is 12 but this number can be easily increased. Furthermore, the resulting implementation outperforms an equivalent desktop-based software implementation (using phylogenetic analysis using parsimony software) by several orders of magnitude. The speed-up values achieved by the hardware implementation on a single node of the Maxwell machine can reach up to four orders of magnitude for the 12-taxa case while implementations on several Maxwell nodes can yield even higher speed-ups. This is achieved through harnessing both coarse-grain and fine-grain parallelism available in the algorithm and corresponding hardware implementation platform.
  • Keywords
    field programmable gate arrays; mainframes; parallel machines; FPGA supercomputer; Maxwell machine; Maxwell nodes; Sankoff´s algorithm; coarse grain; equivalent desktop; field programmable gate array; fine grain; linear systolic array; maximum parsimony; nucleotide sequence data; parsimony software; phylogenetic analysis; reconfigurable hardware; tree topology; Algorithm design and analysis; Field programmable gate arrays; Hardware; Organisms; Parallel processing; Performance analysis; Phylogeny; Supercomputers; Systolic arrays; Topology; Field-programmable gate array (FPGA); high performance computing; maximum parsimony; phylogenetic analysis; reconfigurable hardware;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2009.2039588
  • Filename
    5406016