Two-Dimensional Analysis of Field-Plate Effects on Surface-State-Related Current Transients and Power Slump in GaAs FETs

Author

Horio, Kazushige ; Tanaka, Toshiya ; Itagaki, Keiichi ; Nakajima, Atsushi

Author_Institution

Fac. of Syst. Eng., Shibaura Inst. of Technol., Saitama, Japan

Volume

58

Issue

3

fYear

2011

fDate

3/1/2011 12:00:00 AM

Firstpage

698

Lastpage

703

Abstract

In this paper, we carry out a 2-D transient analysis of field-plate GaAs metal-semiconductor field-effect transistors (FETs) by taking surface states into account. Quasi-pulsed current-voltage curves are derived from the transient characteristics. We show that drain lag and current slump (power slump) due to surface states are reduced by introducing a field plate because the fixed potential at the field plate mitigates the trapping effects of the surface states. The dependence of lag and current slump on the field-plate length and the passivation layer thickness is also studied. We show that it is possible to reduce the current slump and maintain the high-frequency performance of GaAs FETs at optimum values of the field-plate length and the layer thickness.

Keywords

field effect transistors; 2D transient analysis; FET; current slump; drain lag; field plate effect; field plate length; high frequency performance; metal-semiconductor field-effect transistor; passivation layer thickness; power slump; quasi-pulsed current-voltage curve; surface state; surface-state-related current transient; trapping effect; two-dimensional analysis; Drain lag; GaAs field-effect transistor (FET); gate lag; power slump; surface state;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2010.2094621

Filename

5667052