The first IA-64 microprocessor

Author

Rusu, Stefan ; Singer, Gadi

Author_Institution

Intel Corp., Santa Clara, CA, USA

Volume

35

Issue

11

fYear

2000

Firstpage

1539

Lastpage

1544

Abstract

The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set. Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy. The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18-/spl mu/m CMOS process with six metal layers and packaged in a 1012-pad organic land grid array using C4 (flip chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache.

Keywords

CMOS digital integrated circuits; design for testability; integrated circuit design; integrated circuit packaging; microprocessor chips; parallel architectures; 0.18 mum; 1012-pad organic land grid array; 64 bit; 800 MHz; C4 flip chip assembly technology; CMOS process; DFT; IA-32 instruction set; IA-64 architecture; IA-64 microprocessor; L3 cache; OTB domino circuits; binary compatibility; clock distribution methodology; core speed back-side bus; distributed deskew buffers; explicitly parallel instruction computing design; hardware/software synergy; highly parallel execution core; Assembly; CMOS process; Computer aided instruction; Computer architecture; Concurrent computing; Flip chip; Hardware; Microprocessors; Packaging; Software performance;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.881197

Filename

881197