A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors

Author

Chen, Yung-Yuan ; Upadhyaya, Shambhu J. ; Cheng, Ching-Hwa

Author_Institution

Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsin-Chu, Taiwan

Volume

46

Issue

12

fYear

1997

fDate

12/1/1997 12:00:00 AM

Firstpage

1363

Lastpage

1371

Abstract

This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been developed for accurate prediction of yield by considering the effects of defect clusters and switching network failures. This yield simulation tool can also be used to obtain the information on the performance degradation, spare replacement, processor placement, routing and the switch programming algorithm survival probability

Keywords

fault tolerant computing; parallel architectures; reconfigurable architectures; VLSI/WSI; array processors; fault-tolerant; hardware overhead; processor placement; reconfiguration scheme; routing; spare replacement; switch programming; yield simulation; Analytical models; Degradation; Fault tolerance; Logic arrays; Performance analysis; Redundancy; Routing; Switches; Testing; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.641936

Filename

641936