Title :
A 0.18-/spl mu/m 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica
Author :
Kuge, Shigehiro ; Kato, Tetsuo ; Furutani, Kiyohiro ; Kikuda, Shigeru ; Mitsui, Katsuyoshi ; Hamamoto, Takeshi ; Setogawa, Jun ; Hamade, Kei ; Komiya, Yuichiro ; Kawasaki, Satoshi ; Kono, Takashi ; Amano, Teruhiko ; Kubo, Takashi ; Haraguchi, Masaru ; Nak
Author_Institution :
ULSI Dev. Centre, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.
Keywords :
DRAM chips; circuit tuning; delay lock loops; low-power electronics; 0.18 micron; 200 MHz; 256 Mbit; DDR-SDRAM; DLL replica; delay-locked loop; double-data-rate synchronous-DRAM; intra-chip data bus; low-cost post-mold tuning method; Clocks; Costs; Delay lines; Displays; Frequency; Jitter; Logic; Testing; Threshold voltage; Ultra large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
