Novel level-identifying circuit for flash multilevel memories

Author

Montanari, Donato ; Houdt, Jan Van ; Groeseneken, Guido ; Maes, Herman E.

Author_Institution

IMEC, Leuven, Belgium

Volume

33

Issue

7

fYear

1998

fDate

7/1/1998 12:00:00 AM

Firstpage

1090

Lastpage

1095

Abstract

This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current read out from a memory cell and the reference currents that represent the different logic levels. An experimental version of the circuit has been integrated in a standard double-metal 0.7-μm CMOS process with a die area of only 140×100 μm². Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropriate logic level in 9 ns

Keywords

CMOS memory circuits; EPROM; cellular arrays; integrated memory circuits; multivalued logic; 0.7 micron; 5 V; 9 ns; CMOS process; Euclidean distance; analog computation; current read out; die area; flash multilevel memories; level-identifying circuit; logic levels; memory cell; read out operation; reference currents; small-area circuit; Analog computers; CMOS logic circuits; CMOS process; Costs; Euclidean distance; Flash memory; Logic circuits; Logic devices; Power supplies; Silicon;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.701269

Filename

701269