Title :
Design and implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic
Author :
Mateo, Diego ; Rubio, Antonio
Author_Institution :
Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
fDate :
7/1/1998 12:00:00 AM
Abstract :
Adiabatic switching is a technique to design low-power digital IC´s. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is presented, and to validate its performance, a 5×5 ternary digit multiplier is designed and implemented in a 0.7-μm CMOS technology. Results show a satisfactory power saving with respect to conventional and other quasi-adiabatic binary multipliers, and a decrease of the area needed with respect to a fully adiabatic binary one
Keywords :
CMOS logic circuits; integrated circuit design; multiplying circuits; ternary logic; 0.7 micron; CMOS technology; area requirements; power saving; quasi-adiabatic ternary CMOS logic; ternary digit multiplier; CMOS logic circuits; CMOS technology; Clocks; Cost accounting; Inverters; Logic design; Multivalued logic; Power supplies; Silicon; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
