DocumentCode :
1404132
Title :
Reduction of Luminance Errors Due to Line Load in a PDP With Limited Display Levels
Author :
Kim, Jin-Sung ; Won, Jae-Yeon ; Lee, Hyuk-Jae
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
Volume :
6
Issue :
2
fYear :
2010
Firstpage :
65
Lastpage :
74
Abstract :
The displayed level of a plasma display panel (PDP) is often different from the intended level because the luminance of a PDP is affected by the load (i.e., the number of turned-on cells). Previous methods have attempted to reduce the difference by predicting the luminance variation and compensating for the difference. The luminance prediction and error compensation are difficult with a PDP that displays a limited number of gray levels. This paper proposes a novel luminance prediction and error compensation algorithm for a PDP with limited display levels. It overcomes the shortcomings of the previous method by avoiding the gray errors caused by the luminance reverse that occurs when the luminance of a lower sub-field becomes larger than that of a higher sub-field. Furthermore, the prediction accuracy is improved by two additional schemes, load stabilization and prediction. The mean absolute error and maximum error of the proposed algorithm are reduced by 23.2% and 31.9%, respectively, compared with the previous method.
Keywords :
brightness; error correction; plasma displays; PDP; error compensation algorithm; limited display levels; load prediction; load stabilization; luminance error reduction; luminance variation; plasma display panel; Accuracy; Degradation; Digital-to-frequency converters; Error compensation; Error correction; Image quality; Image resolution; Load management; Plasma displays; TV; Error correction; halftoning; luminance error; plasma display panel (PDP); subfield coding;
fLanguage :
English
Journal_Title :
Display Technology, Journal of
Publisher :
ieee
ISSN :
1551-319X
Type :
jour
DOI :
10.1109/JDT.2009.2032134
Filename :
5406173
Link To Document :
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