Title :
Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees
Author :
Doménech-Asensi, G. ; Kazmierski, T.J. ; Ruiz-Marin, J.D. ; Ruiz-Merino, R.
Author_Institution :
Dept. de Electron., Tecnologia de Computadoras y Proyectos, Univ. Politecnica de Cartagena, Spain
fDate :
9/28/2000 12:00:00 AM
Abstract :
A technique of translating high-level analogue dynamic system behavioural models from VHDL-AMS parse trees into circuit-level netlists is described. The primary application of this work is automatic synthesis of general analogue dynamic systems with feedback. The technique is demonstrated with a practical example of Lorenz`s chaos system synthesis
Keywords :
analogue integrated circuits; hardware description languages; high level synthesis; integrated circuit design; mixed analogue-digital integrated circuits; ASIC design; CAD; Lorenz chaos system synthesis; analogue VHDL-AMS descriptions; architectural synthesis; automatic synthesis; circuit-level netlists; dynamic system behavioural models; feedback; general analogue dynamic systems; high-level VHDL-AMS descriptions; netlist extraction; parse trees;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20001202
