Low-speed scan testing of charge-sharing faults for CMOS domino circuits

Domino circuits have been widely used to design high-performance processors. However, domino logic suffers from the problem of charge-sharing, which may degrade the output voltage level or even cause an erroneous output value (charge-sharing fault). It is shown that charge-sharing faults are resistant to scan testing and that a killing error might occur because of the low-speed testing problem caused by scan testing. The testing error is investigated and a DFT technique to efficiently eliminate this problem is proposed