Double-layer process for wide gate recess etch

The technique uses a double layer of standard polymethyl methacrylate (PMMA) electron resist and a sensitive copolymer of PMMA. With this technique, the width of the recess (and hence the gate edge to n⁺ layer distance d_c) can be controlled by using different developers or by altering the ratio of polymers in the bottom layer. A numerical technique is used to model the breakdown voltage of FETs having different gate recess widths, which indicates that the optimum distance d_c is in the range of 0.2 to 0.7 μm, depending on the thickness of the channel layer