Title :
On Modulo 2^n+1 Adder Design
Author :
Vergos, Haridimos T. ; Dimitrakopoulos, Giorgos
Author_Institution :
Dept. of Comput. Eng. & Inf., Univ. of Patras, Patras, Greece
Abstract :
Two architectures for modulo 2n+1 adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2n+1 addition. This sparse approach is enabled by the introduction of the inverted circular idempotency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished-1 adders can be implemented in smaller area and consume less power compared to all earlier proposals, while maintaining a high operation speed. The second architecture unifies the design of modulo 2n ± 1 adders. It is shown that modulo 2n+1 adders can be easily derived by straightforward modifications of modulo 2n-1 adders with minor hardware overhead.
Keywords :
adders; carry logic; parallel architectures; power aware computing; residue number systems; diminished-1 adders; inverted circular idempotency property; modulo 2n+1 adder architecture; modulo 2n+1 adder design; parallel-prefix carry operator; sparse carry computation unit; Adders; Bismuth; Complexity theory; Computer architecture; Delay; Informatics; Proposals; Modulo arithmetic; VLSI.; computer arithmetic; parallel-prefix carry computation; residue number system (RNS);
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.2010.261
