DocumentCode
1405779
Title
The path-status graph with application to delay fault simulation
Author
Gharaybeh, Marwan A. ; Bushnell, Michael L. ; Agrawal, Vishwani D.
Author_Institution
CAIP Center, Rutgers Univ., Piscataway, NJ, USA
Volume
17
Issue
4
fYear
1998
fDate
4/1/1998 12:00:00 AM
Firstpage
324
Lastpage
332
Abstract
We present an efficient path-delay fault (PDF) simulator that does not involve the enumeration of paths. Our method calculates the exact fault coverage, and identifies all tested faults in any circuit with a large number of paths. We present a new data structure, called the path-status graph (PSG), to efficiently hold the status of each PDF in the circuit, i.e., whether or not the PDF is tested. The keg to this efficiency is in breaking the information into pieces and distributing it over the data structure, and in retaining all or part of the reconverging fan-out structure of the circuit in the PSG. Thus, an exponential number of PDF´s can share the same piece of information. Using 1000 random tests, we simulated all of the approximately 1020 PDF´s in the circuit c6288, and determined that 4.4 billion faults were detected. This number is larger by over three orders of magnitude compared to what was possible with previously reported methods
Keywords
circuit analysis computing; data structures; delays; fault diagnosis; graph theory; data structure; delay fault simulation; fault coverage calculation; path-status graph; reconverging fan-out structure; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer industry; Data structures; Delay; Fault detection; Space technology;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.703822
Filename
703822
Link To Document