• DocumentCode
    1406202
  • Title

    Unified Compact Model of Soft Breakdown Oxide Degradation and Its Impact on CMOS Circuits Reliability

  • Author

    Gerrer, Louis ; Ghibaudo, Gérard ; Rafik, Mustapha

  • Author_Institution
    LAHC, IMEP, Grenoble, France
  • Volume
    12
  • Issue
    1
  • fYear
    2012
  • fDate
    3/1/2012 12:00:00 AM
  • Firstpage
    171
  • Lastpage
    176
  • Abstract
    Oxide breakdown (BD) modeling may allow important reliability margin extension since the BD has been shown to be not immediately destructive for circuit operation. BD characterization and understanding are strongly required to implement relevant models, reproducing all BD parameter deviations. Owing to damaged device characterization, we extract empirical laws of BD impact evolution and implement them in the first BD damaged compact model. Parameter variability correlation is explained through measurements and simulations, particularly threshold voltage deviation due to BD. Using our original compact model, we investigate BD impacts on circuit functioning, showing original effects and several improvements of previous studies. Inverter threshold, power consumption increase, BD path location impact, and SRAM cell SNM reduction are examined, demonstrating the ability of our compact model to estimate circuit lifetime extension, including circuit parameter deviations.
  • Keywords
    CMOS memory circuits; SRAM chips; electric breakdown; integrated circuit modelling; integrated circuit reliability; BD characterization; BD impact evolution; BD modeling; BD parameter deviations; BD path location impact; BD-damaged compact model; CMOS circuit reliability; SRAM cell SNM reduction; circuit functioning; circuit lifetime extension; circuit operation; circuit parameter deviations; inverter threshold; oxide breakdown modeling; parameter variability correlation; power consumption; reliability margin extension; soft-breakdown oxide degradation; threshold voltage deviation; unified-compact model; Electric breakdown; Integrated circuit modeling; Inverters; Logic gates; MOS devices; Random access memory; Threshold voltage; Breakdown evolution; channel debiasing; current partitioning methodology; dielectric breakdown;
  • fLanguage
    English
  • Journal_Title
    Device and Materials Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1530-4388
  • Type

    jour

  • DOI
    10.1109/TDMR.2011.2181174
  • Filename
    6111463