Solder bump reliability-issues on bump layout

Author

Alander, Tapani ; Heino, Pekka ; Ristolainen, Eero

Author_Institution

Inst. of Electron., Tampere Univ. of Technol., Finland

Volume

23

Issue

4

fYear

2000

fDate

11/1/2000 12:00:00 AM

Firstpage

715

Lastpage

720

Abstract

The reliability of solder bumps in a typical under-filled flip chip package is calculated three-dimensionally (3-D) using the finite element method and a viscoplastic material model for the solder. Simulations are performed with varying bump placement, underfill coverage and board size. The average plastic work in a bump is used to compare the loading and bump reliability of different geometries. The results show possible improvements over the traditional bump placement by changing the geometry of the interconnects on the flip chip package. Three changes that improve reliability are discussed in detail: the redistribution of bump rows, the reduction of board size and the inclusion of heat transfer bumps.

Keywords

finite element analysis; flip-chip devices; integrated circuit packaging; integrated circuit reliability; soldering; viscoplasticity; board size; bump layout; bump placement; bump reliability; bump rows; finite element method; heat transfer bumps; solder bump reliability; under-filled flip chip package; underfill coverage; viscoplastic material model; Bonding; Capacitive sensors; Flip chip; Geometry; Joining materials; Materials reliability; Packaging; Plastics; Strain measurement; Temperature;

fLanguage

English

Journal_Title

Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1521-3323

Type

jour

DOI

10.1109/6040.883763

Filename

883763