Title :
Design and implementation of a novel linear-array DCT/IDCT processor with complexity of order log2N
Author :
Hsiao, S.-F. ; Hiue, W.R. ; Tseng, J.-M.
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fDate :
10/1/2000 12:00:00 AM
Abstract :
A new linear-array architecture for computation of both the discrete cosine transform (DCT) and the inverse DCT (IDCT) is derived from the heterogeneous dependence graphs representing the factorised coefficient matrices in the matrix formulation of the recursive algorithm. Using the Kronecker product representation of the order-recursive algorithm, it is observed that the kernel operations of the DCT and IDCT can be merged together by proper input/output data reordering. The processor containing only O(log2N) stages is fully pipelineable and easily scaleable to compute longer DCT/IDCTs with transform length N to the power of two. Owing to the systematic matrix formulation and the corresponding efficient architectural design, the new DCT/IDCT processor has the advantages of high-throughput rate and low hardware cost. Furthermore, the power consumption can be reduced significantly by turning off the operation of the arithmetic units whenever possible
Keywords :
VLSI; computational complexity; digital signal processing chips; discrete cosine transforms; inverse problems; matrix algebra; parallel processing; Kronecker product representation; VLSI; arithmetic units; complexity; discrete cosine transform; efficient architectural design; factorised coefficient matrices; fast recursive DCT/IDCT algorithm; heterogeneous dependence graphs; high-throughput rate; input/output data reordering; inverse DCT; kernel operations; linear-array DCT/IDCT processor; linear-array architecture; low hardware cost; matrix formulation; order-recursive algorithm; pipeline processor; power consumption reduction; recursive algorithm; transform length;
Journal_Title :
Vision, Image and Signal Processing, IEE Proceedings -
DOI :
10.1049/ip-vis:20000471
