Band-to-band tunneling and thermal generation gate-induced drain leakage

MOSFET oxide scaling for DRAM (dynamic random-access memory) applications can be limited by gate-induced diode leakage, which has been shown previously by experiments at cryogenic temperatures to consist of a thermal volume generation and a band-to-band tunneling mechanism. Tunneling is the dominant mechanism at relatively higher voltages and cryogenic temperatures. The authors have studied the leakage as a function of low applied bias and made low-temperature measurements (25 K to 400 K) of this mechanism, using a submicrometer N ⁺ polysilicon gate CMOS process. They have also studied the tunnel current dependence on gate-to-drain bias, dielectric thickness, gate-to-drain overlap, flatband voltage and bandgap narrowing for n- and p-channel devices. Experimentally the leakage current characteristic satisfies an exp(-B/E_s) relationship, where E_s is the electric field at the silicon dioxide-silicon interface. The coefficient B contains the tunneling temperature dependence. The leakage current has strong oxide-thickness, flatband, and voltage dependencies. By withdrawing the diffusion edge, thereby reducing the overlap area, the tunnel current decreases and has a gate voltage dependency. The gated-diode leakage impact on MOSFET dielectric scaling can be reduced by scaling gate-to-diffusion overlap