Design and Analysis of a Class-D Stage With Harmonic Suppression

Author

Fritzin, Jonas ; Svensson, Christer ; Alvandpour, Atila

Author_Institution

Dept. of Electr. Eng., Linkoping Univ., Linkoping, Sweden

Volume

59

Issue

6

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

1178

Lastpage

1186

Abstract

This paper presents the design and analysis of a low-power Class-D stage in 90 nm CMOS featuring a harmonic suppression technique, which cancels the 3rd harmonic by shaping the output voltage waveform. Only digital circuits are used and the short-circuit current present in Class-D inverter-based output stages is eliminated, relaxing the buffer requirements. Using buffers with reduced drive strength for the output stage reduces the 5th harmonic at the output, as the rise and fall time of the output voltage increase. Operating at 900 MHz, the measured output power was +5.1 dBm with drain efficiency (DE) and power-added efficiency (PAE) of 73% and 59% at 1.2 V. The 3rd and 5th harmonics were suppressed by 34 dB and 4 dB, respectively, compared to an inverter-based Class-D stage.

Keywords

CMOS digital integrated circuits; harmonics suppression; invertors; low-power electronics; CMOS; Class-D inverter; complementary metal-oxide-semiconductor; digital circuits; frequency 900 MHz; harmonic suppression; low-power Class-D stage; power-added efficiency; short-circuit current; size 90 nm; voltage 1.2 V; Capacitance; Capacitors; Harmonic analysis; Harmonics suppression; Power generation; Power system harmonics; Transistors; CMOS; Radio transmitter; harmonic rejection;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2011.2173389

Filename

6112187