A Multidrop Bus Design Scheme With Resistor-Based Impedance Matching on Nonuniform Impedance Lines

In this paper, a bus design scheme that achieves both impedance matching and uniform power distribution for a multidrop bus is presented. In contrast to conventional schemes, the proposed scheme lets the line impedance of each segment of the bus vary, and the impedance-matching resistance values are determined accordingly, thereby providing higher degrees of freedom for optimization. General formulas for determining the optimal line impedances and matching resistances are derived. The voltage and power ratios between the master driver and branch receivers are also established, showing that such ratios depend only on the master-to-branch impedance ratio and the number of branches. Similar relations are also derived for the backward direction. The measurement results of the fabricated FR4 printed circuit boards demonstrate good agreement with the theoretical results, and show reliable performance up to a bit rate of 5 Gbps.